Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same

ABSTRACT

Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a thin film transistor array panel fora liquid crystal display and a method for manufacturing the same,especially to a method for manufacturing a thin film transistor arraypanel with a reduced number of photolithography steps.

(b) Description of the Related Art

A liquid crystal display (LCD) is one of the most popular FPDs (flatpanel displays). The LCD has two panels having electrodes for generatingelectric fields and a liquid crystal layer interposed therebetween. Thetransmittance of incident light is controlled by the intensity of theelectric field applied to the liquid crystal layer.

In the most widely used LCD, the field-generating electrodes areprovided at both panels, and one of the panels has switching elementssuch as thin film transistors (TFTs).

In general, a thin film transistor array panel is manufactured byphotolithography using a plurality of photomasks, and five or sixphotolithography steps are used. The high cost for the photolithographyprocess makes it desirable to reduce the number of the photolithographysteps. Even though a few manufacturing methods using only fourphotolithography steps are suggested, these methods are not easy toaccomplish.

Now, a conventional method of manufacturing a thin film transistor arraypanel using four lithography steps will be described.

First, a gate wire of aluminum or aluminum alloy are formed on asubstrate by using a first mask. A gate insulating layer, an amorphoussilicon layer, an n+ amorphous silicon layer and a metal layer aresequentially deposited. The metal layer, the n+ amorphous silicon andthe amorphous silicon layer are patterned by using a second mask. Atthis time, gate pads of the gate wire is covered only with the gateinsulating layer. An ITO (indium tin oxide) layer is deposited andpatterned by using a third mask. At this time, the portions of the ITOlayer over the gate pads are removed. After the metal layer and the n+amorphous silicon layer thereunder are patterned by using the patternedITO layer as an etch mask, a passivation layer is deposited. A completethin film transistor array panel is obtained by patterning thepassivation layer and gate insulating layer thereunder using a fourthmask, thereby removing the portion of the passivation layer and the gateinsulating layer on the gate pads.

As a result, the gate pads of aluminum or aluminum alloy are exposed inthe conventional manufacturing method of using four masks. The aluminumand the aluminum alloy cannot stand against physical and chemicalvariations and are vulnerable to damage and oxidation, despite theiradvantages of low resistivity. To compensate this matter, gate lines areformed to have multiple-layered structure or made of materials that canstand against the physical and chemical changes. However, the formermakes the manufacturing process complicated, and the latter may resultin a high resistivity problem.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide newmethods for manufacturing a thin film transistor array panel for LCDswith a reduced number of photolithography steps.

It is another object of the present invention to protect gate pads ofLCDs.

It is the other object of the present invention to prevent the LCD'scurrent leakage.

These and other objects are achieved, according to the presentinvention, by patterning the gate insulating layer, the semiconductorlayer, the ohmic contact layer and the data conductor layer at a time.

According to the present invention, a gate wire is formed on aninsulating substrate by a first photolithography process. A quadruplelayers including a gate insulating layer, a semiconductor layer, anohmic contact layer and a data conductor layer is deposited on theinsulating substrate and the gate wire and formed by a secondphotolithography process. A conductive pattern is formed on the dataconductor layer and the area surrounded by the data conductor layer by athird photolithography process. Then, the portion of the data conductorlayer not covered by the conductive pattern is etched out to form a datawire and the ohmic contact layer not covered by the data wire is alsoetched out. Finally, a passivation layer pattern on the conductivepattern is formed by a fourth photolithography process.

At this time, the gate wire may include a plurality of gate linesextended to a first direction, gate electrodes that are branches of thegate line and gate pads connected to an end of the gate line andreceiving a scanning signal from an external circuit, The quadruplelayers may have first contact holes exposing the gate pad, and thepassivation layer may have second contact holes exposing the firstcontact hole.

The gate wire may include a plurality of gate lines extended to a firstdirection, gate electrodes that are branches of the gate line and gatepads connected to an end of the gate line and receiving a scanningsignal from an external circuit. The quadruple layers may have firstcontact holes exposing the gate pad. The conductive pattern may includefirst conductive patterns connected to the gate pad through the firstcontact hole, and the passivation layer may have second contact holesexposing the first conductive pattern.

The gate wire may include a plurality of gate lines extended to a firstdirection, gate electrodes that are branches of the gate line and gatepads connected to an end of the gate line and receiving a scanningsignal from an external circuit. The data wire may include a pluralityof data lines extended to a second direction and crossing the gate line,data pads connected to an end of the data line and receiving an imagesignal from an external circuit, source electrodes connected to the dataline and adjacent with the gate electrode, and drain electrodes locatedat the opposite side of the source electrode with respect to the gateelectrode. The conductive pattern may include a plurality of firstconductive patterns formed on the data line, the source electrode andthe data pad, second conductive patterns formed on the drain electrode,and pixel electrodes connected to the second conductive pattern andformed in the area surrounded by the gate line and the data line. Thepassivation layer may have first openings exposing the pixel electrodeand second openings exposing the first conductive pattern on the datapad. The passivation layer may have third openings exposing a part ofthe semiconductor layer between the adjacent two data line. The step mayfurther comprise a step of etching the exposed portion of thesemiconductor layer to separate the semiconductor layer under the twodata line from each other. The pixel electrode may be overlapped withthe previous gate line and the portion of the semiconductor layersandwiched between the pixel electrode and the gate line is isolatedfrom the other portion.

The gate insulating layer may include a first portion formed between thegate pads and between the data pads, the passivation layer may have afourth opening exposing the first portion of the gate insulating layer.The portion of the semiconductor layer located on the first portion ofthe gate insulating layer may be removed to separate the portions of thesemiconductor layer under the gate pads and the data pads.

The passivation layer may cover the edge of the pixel electrode. Thefirst opening exposes the edge of the pixel electrode. A storage wireoverlapped with the pixel electrode may be formed on the substrate, thequadruple layers may be formed on the storage wire, and the portion ofthe semiconductor layer sandwiched between the storage wire and thepixel electrode is isolated from the other portion.

The passivation layer may have a trench exposing the portion of thesemiconductor layer between the first conductive pattern and the pixelelectrode and between the adjacent pixel electrodes, and furthercomprising a step of etching the exposed semiconductor layer through thetrench. The gate line may include two main lines and branches connectingthe two main lines, and the pixel electrode may be overlapped with apart of the gate line. The source electrode may have a concave part andthe end part of the drain electrode may be located in the concave part.

The conductive pattern may be made of a transparent conductor such asindium-tin-oxide.

The forming step of the quadruple layers may comprise the substeps ofcoating a photoresist layer on the data conductor layer, patterning thephotoresist layer to be a pattern of which thickness is varyingdepending on the location by exposure and development, etching thequadruple layers along with the photoresist layer pattern to expose thegate pad, to form a data wire leaving the source electrode and the drainelectrode connected to each other, and to expose the portion of the gateinsulating layer between the data wires. A first portion, the thinnestportion of the photoresist layer, may be formed on the gate pad. Asecond portion, the thickest portion, may be formed on the data wirewhere the source electrode and the drain electrode are connected to eachother. A third portion that is thicker than the first portion andthinner than the second portion may be formed between the secondportions. The exposure of the photoresist layer may be performed byusing a photomask having at least three parts of which transmittance aredifferent from each other. A portion of the gate insulating layer may beremoved to expose ends of the gate wire by the second photolithographyprocess. The conductive pattern may include first conductive patternscontacting with the exposed end of the gate wire. Contact holes exposingthe first conductive pattern may be formed in the passivation layer bythe fourth photolithography process.

According to the present invention, a thin film transistor array panelis provided. The thin film transistor array panel comprises a gate wireformed on an insulating substrate and including a plurality of gatelines extending to a first direction, gate electrodes connected to thegate line, and gate pads connected to an end of the gate line, a gateinsulating layer having contact holes exposing the gate pad and formedin a matrix shape on the gate wire and the substrate, a semiconductorlayer formed on the gate insulating layer, a data wire formed on thesemiconductor layer and including a plurality of data lines extending toa second direction to cross the gate line, source electrodes adjacent tothe gate electrode, drain electrode separated from the data line and thesource electrode and located at the opposite side of the sourceelectrode with respect to the gate electrode, and data pads connected toan end of the data line, a conductive pattern including a plurality offirst patterns formed on the source electrode and the data line, secondpatterns formed on the drain electrode, third patterns formed on thedata pad, and pixel electrodes connected to the second pattern, and apassivation layer formed on the conductive pattern, the semiconductorpattern and the substrate, and having a plurality of first openingsexposing the pixel electrode, second openings exposing the gateinsulating layer between the two adjacent data lines, third openingslocated on the gate pad, and fourth openings exposing the third pattern.At this time, the data wire is only formed between the conductivepattern and the semiconductor layer, the semiconductor layer is formedon the whole gate insulating layer except the portion under the secondopening, and the portions of the semiconductor layer under the twoadjacent data lines are separated from each other.

At this time, the thin film transistor array panel may further comprisea contact layer formed between the semiconductor layer and the data wireto have the same layout as the data wire and to reduce the contactresistance between the semiconductor layer and the data wire. Theconductive pattern further includes a fourth pattern connected to thegate pad through the contact hole and the third opening exposes thefourth pattern. The pixel electrode may be overlapped with the adjacentgate line and the portion of the semiconductor layer sandwiched betweenthe pixel electrode and the gate line is isolated from the otherportion. The gate insulating layer may include a first portion formedbetween the two gate pads and the two data pads, the passivation layerhas fifth openings exposing the first portion of the gate insulatinglayer, and the semiconductor layer is not formed under the fifthopening. The passivation layer may cover the edge of the pixelelectrode. The first opening may expose the edge of the pixel electrode.The thin film transistor array panel may further include a storage wireformed on the substrate, overlapped with the pixel electrode and coveredby the gate insulating layer, wherein the portion of the semiconductorlayer sandwiched between the storage wire and the pixel electrode isisolated from the other portion. The conductive pattern may be made ofindium-tin-oxide.

According to the present invention, a thin film transistor array panelmay be manufactured by a method comprising the steps of forming a gatewire including a plurality of gate lines and gate pads by a firstphotolithography process. The next step is depositing a first insulatinglayer, a semiconductor layer, an ohmic contact layer and a metal layeron the gate wire and forming a metal layer pattern, an ohmic contactlayer pattern, a semiconductor layer pattern and a first insulatinglayer pattern that have a matrix shape layout overlapping the gate wireexcept the gate pad by a second photolithography process. The next stepis depositing a transparent conductor layer, forming a transparentconductor pattern including a pixel electrode, a plurality of redundantdata lines, redundant source electrodes, redundant drain electrodes,redundant data pads and redundant gate pads by a third photolithographyprocess. Following is etching out the portion of the metal layer notcovered by the transparent conductor pattern and the ohmic contact layerthereunder, depositing a second insulating layer, forming a passivationlayer pattern having openings respectively exposing the gate pad, thedata pad, the pixel electrode and the portion of the semiconductor layerconnecting the adjacent data line, and etching out the portion of thesemiconductor layer exposed through the openings.

At this time, the manufacturing method may further comprise an etchingstep of the first insulating layer under the exposed portion of thesemiconductor layer after the etching step of the exposed portion of thesemiconductor layer.

According to the present invention, a thin film transistor array panelmay also be manufactured by a method comprising the steps of forming agate wire including a plurality of gate lines and gate pads by a firstphotolithography process. The next step is depositing a first insulatinglayer, a semiconductor layer, an ohmic contact layer and a metal layeron the gate wire and patterning the metal layer, the ohmic contactlayer, the semiconductor layer and the first insulating layer to form ametal layer pattern, an ohmic contact layer pattern and a semiconductorlayer pattern that are separated into two pieces at least on the gatewire and a first insulating layer pattern covering the gate wire exceptfor the gate pad. The following step is depositing a transparentconductor layer and forming a transparent conductor layer pattern by athird photolithography process. The next step is etching the portion ofthe metal layer not covered by the transparent conductor layer patternand the ohmic contact layer thereunder. The final step is to form a datawire including a plurality of data pads, source and drain electrodes andohmic contact layer pattern thereunder, depositing a second insulatinglayer, and forming a passivation layer pattern at least having contactholes exposing the gate pad and the data pad by a fourthphotolithography process.

At this time, the second photolithography process may comprise thesubsteps of coating a photoresist layer on the metal layer, forming aphotoresist layer pattern having at least three portions of whichthickness are different from each other by exposure and development, andetching the metal layer, the ohmic contact layer, the semiconductorlayer and the first insulating layer along with the photoresist layer toremove the first portion that is the thinnest portion of the photoresistlayer pattern, and the metal layer, the ohmic contact layer, thesemiconductor layer and the first insulating layer thereunder, alongwith the third portion that is thicker than the first portion, and themetal layer, the ohmic contact layer and the semiconductor layerthereunder, but not to remove the layers under the second portion whichis the thickest portion. The exposure of the photoresist layer may beperformed by using a photomask including at least three parts of whichtransmittance are different from each other. The photomask may haveslits smaller than the resolution of the stepper or is formed by atleast two materials of which transmittance are different from eachother. The photomask may be classified into a first mask to form thegate pad and a second mask to form the other area and the transmittanceof the first mask is different from that of the second mask. The firstportion of the photoresist layer pattern may be located on the gate pad.

The etching step of the metal layer, the ohmic contact layer and thefirst insulating layer along with the photoresist layer pattern maycomprise the substeps of etching the metal layer, the ohmic contactlayer, the semiconductor layer and the first insulating layer under thefirst portion of the photoresist layer pattern by using the second andthe third portion as-an etch stopper, removing the second portion of thephotoresist layer to expose the metal layer thereunder by ashingprocess, and etching the exposed portion of the metal layer, and theohmic contact layer and the semiconductor layer thereunder by using thethird portion of the photoresist layer as an etch stopper.

The semiconductor layer may be made of amorphous silicon. The secondinsulating layer may be made of a photo-definable material.

According to the present invention, a thin film transistor array panelmay be manufactured by a method comprising the steps of forming a gatewire including a plurality of gate lines and a plurality of gate padsconnected to the gate lines on a substrate having a display area and aperipheral area, the gate lines located substantially in the displayarea and the gate pads located substantially in the peripheral area. Thenext step is sequentially depositing a gate insulating layer, asemiconductor layer, an ohmic contact layer and a conductor layer on thegate wire, coating a photoresist layer on the metal layer, forming aphotoresist layer pattern of which thickness is varying depending on thelocation by exposure and development, patterning the metal layer, theohmic contact layer, the semiconductor layer and the gate insulatinglayer at a time to form a metal layer pattern, a first ohmic contactlayer pattern and a semiconductor layer pattern and expose the gate padby a photolithography process. The following step is depositing aconductor layer, forming a conductor layer pattern including a pixelelectrode covering a part of the metal layer and a separated conductorlayer pattern covering the other part of the metal layer and located atthe opposite side of the pixel electrode with respect to the gateelectrode by a photolithography process. The next step is removing theportion of the metal layer between the pixel electrode and the separatedconductor layer pattern and the ohmic contact layer thereunder to form adata wire including a plurality of data lines, data pads, sourceelectrodes and drain electrodes, and a second ohmic contact layerpattern thereunder. And the final step is forming a passivation layer.

At this time, the photoresist layer pattern may be formed only in thedisplay area and on the metal layer pattern, the thickness of thephotoresist layer pattern is thicker on the metal layer pattern thanelsewhere of the display area. The step of patterning the metal layer,the ohmic contact layer, the semiconductor layer and the gate insulatinglayer at a time may comprise the substeps of removing the exposedportion of the metal layer in the peripheral area to expose the ohmiccontact layer, removing the thin photoresist layer in the display areato expose the metal layer thereunder by using an etch method that isable to etch the photoresist layer, the ohmic contact layer and thesemiconductor layer at a time. Then, the exposed portion of the metallayer in the display area is removed to expose the ohmic contact layer.The semiconductor layer and the gate insulating layer are etched out toexpose the gate pad in the peripheral area and to remove the exposedportion of the ohmic contact layer and the semiconductor layerthereunder by using an etch method that is able to etch the ohmiccontact layer, the semiconductor layer and the gate insulating layer ata time.

The passivation layer may have openings exposing the pixel electrode.The conductor layer pattern may include a plurality of redundant datalines covering the data line, redundant data pad covering the data padand redundant gate pad covering the gate pad. The passivation layer mayhave openings exposing the redundant gate pad and the redundant datapad. The manufacturing method may further include a step of forming acommon wire on the substrate including a plurality of common electrodesthat generate electric fields with the pixel electrode.

According to the present invention, a thin film transistor array panelmay be manufactured by a method comprising the steps of forming a gatewire including a plurality of gate lines, gate electrodes connected tothe gate line and a common wire including a plurality of commonelectrodes on an insulating substrate, forming a gate insulating layerpattern that covers the gate wire and the common wire, forming asemiconductor pattern on the gate insulating layer, forming an ohmiccontact layer pattern on the semiconductor pattern, forming a data wireincluding a plurality of data lines, source electrodes connected to thedata line, drain electrodes separated from the source electrode on theohmic contact layer pattern, forming a passivation layer patterncovering the data wire except for a part of the drain electrode, andforming a plurality of pixel electrode connected to the drain electrodesand generating electric fields with the common electrode. At this time,the source electrode and the drain electrode is separated by aphotolithography process that uses a photoresist layer pattern. Thephotoresist layer pattern includes a first portion located between thesource electrode and the drain electrode, a second portion thicker thanthe first portion, and a third portion thinner than the first portion.

Furthermore, the data wire, the ohmic contact layer and thesemiconductor layer may be formed using a mask. The gate insulatinglayer, the semiconductor pattern, the ohmic contact layer pattern andthe data wire may be formed in the substeps of depositing the gateinsulating layer, the semiconductor layer, the ohmic contact layer andthe metal layer. A photoresist layer is coated on the metal layer andexposed through the photomask. Then, the photoresist layer is developedto form the photoresist layer pattern. The second portion of the patternis located on the data wire. The portion of the metal layer, the ohmiccontact layer and the semiconductor layer under the third portion areetched out. The second portion is also etched to a certain thicknessalong with the portion of the metal layer and the ohmic contact layerthereunder. The remaining photoresist layer pattern of the secondportion is used for forming the data wire, the ohmic contact layerpattern and the semiconductor pattern. Finally, the photoresist layerpattern is removed. The data wire, the ohmic contact layer pattern andthe semiconductor pattern may be formed in the substeps of etching theportion of the metal layer under the third portion to expose the ohmiccontact layer by wet etch or dry etch, dry etching the ohmic contactlayer under the third portion and the semiconductor layer thereunderalong with the first portion to expose the gate insulating layer underthe third portion and the metal layer under the first portion along withcompleting the semiconductor pattern. The portion of the metal layerunder the first portion and the ohmic contact layer thereunder areetched out to complete the data wire and the ohmic contact layerpattern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a substrate partitioned to manufacture a TFTpanel for an LCD according to an embodiment of the present invention.

FIG. 2 is a layout view of a TFT panel for an LCD according to anembodiment of the present invention.

FIG. 3 is a layout view of a TFT panel for an LCD according to the firstembodiment of the present invention, and an enlarged view of a portionmainly including a pixel and pads of the FIG. 2.

FIGS. 4 and 5 are cross-sectional views respectively taken along theline IV-IV′ and V-V′ of the FIG. 3.

FIG. 6A is a layout view of a TFT panel in the first manufacturing stepaccording to the first embodiment of the present invention.

FIGS. 6B and 6C are respectively the cross-sectional views taken alongthe line VIB-VIB′ and VIC-VIC′ of the FIG. 6A.

FIG. 7A is a layout view of a TFT panel in a manufacturing stepfollowing the FIGS. 6A to 6C.

FIGS. 7B and 7C are respectively the cross-sectional views taken alongthe line VIIB-VIIB′ and VIIC-VIIC′ of the FIG. 7A.

FIG. 8A is a layout view of a TFT panel in a manufacturing stepfollowing the FIGS. 7A to 7C.

FIGS. 8B and 8C are respectively the cross-sectional views taken alongthe line VIIIB-VIIIB′ and VIIIC-VIIIC′ of the FIG. 8A.

FIG. 9 is a layout view of a TFT panel for an LCD according to thesecond embodiment of the present invention, and an enlarged view of aportion mainly including a pixel and pads of the FIG. 2.

FIGS. 10 and 11 are cross-sectional views respectively taken along theline X-X′ and XI-XI′ of the FIG. 9.

FIG. 12A is a layout view of a TFT panel in the first manufacturing stepaccording to the second embodiment of the present invention.

FIG. 12B is the cross-sectional view taken along the line XIIB-XIIB′ ofthe FIG. 12A.

FIG. 13A is a layout view of a TFT panel in a manufacturing stepfollowing the FIGS. 12A and 12B.

FIG. 13B is the cross-sectional view taken along the line XIIIB-XIIIB′of the FIG. 13A.

FIG. 14 is a layout view of a TFT panel for an LCD according to thethird embodiment of the present invention, and an enlarged view of aportion mainly including a pixel and pads of the FIG. 2.

FIG. 15 is a cross-sectional view taken along the line XV-XV′ of theFIG. 14.

FIG. 16 is a layout view of a TFT panel for an LCD according to thefourth embodiment of the present invention, and an enlarged view of aportion mainly including a pixel and pads of the FIG. 2.

FIGS. 17 and 18 are cross-sectional views respectively taken along theline XVII-XVII′, XVIII-XVIII′ of the FIG. 16.

FIG. 19 is a layout view of a TFT panel for an LCD according to thefifth embodiment of the present invention, and an enlarged view of aportion mainly including a pixel of the FIG. 2.

FIG. 20 is a cross-sectional view taken along the line XX-XX′ of theFIG. 19.

FIG. 21 is a layout view of a TFT panel for an LCD according to thesixth embodiment of the present invention, and an enlarged view of aportion mainly including a pixel and pads of the FIG. 2.

FIG. 22 is a cross-sectional view taken along the line XXII-XXII′ of theFIG. 21.

FIG. 23A is a layout view of a TFT panel in the first manufacturing stepaccording to the sixth embodiment of the present invention.

FIG. 23B is the cross-sectional view taken along the line XXIIIB-XXIIIB′of the FIG. 23A.

FIG. 24A is a layout view of a TFT panel in a manufacturing step next tothe FIGS. 23A and 23B.

FIG. 24B is the cross-sectional view taken along the line XXIVB-XXIVB′of the FIG. 24A.

FIGS. 25A and 25B, FIGS. 26A and 26B and FIG. 27 are respectivelycross-sectional views of photomasks used in the manufacturing step ofFIGS. 24A and 24B.

FIG. 28 is the cross-sectional view taken along the line XXIVB-XXIVB′ ofthe FIG. 24A in the manufacturing step following the FIG. 24B.

FIG. 29A is a layout view of a TFT panel in a manufacturing stepfollowing the FIG. 28.

FIG. 29B is the cross-sectional view taken along the line XXIXB-XXIXB′of the FIG. 29A.

FIG. 30 is a layout view of a TFT panel for an LCD according to theseventh embodiment of the present invention.

FIGS. 31 and 32 are cross-sectional views respectively taken along theline XXXI-XXXI′ and XXXII-XXXII′ of the FIG. 30.

FIG. 33A is a layout view of a TFT panel in the first manufacturing stepaccording to the seventh embodiment of the present invention.

FIGS. 33B and 33C are respectively the cross-sectional views taken alongthe line XXXIIIB-XXXIIIB′ and XXXIIIC-XXXIIIC′ of the FIG. 33A.

FIG. 34A is a layout view of a TFT panel in a manufacturing stepfollowing the FIGS. 33A to 33C.

FIGS. 34B and 34C are respectively the cross-sectional views taken alongthe line XXXIVB-XXXIVB′ and XXXIVC-XXXIVC′ of the FIG. 34A.

FIG. 35A is a layout view of a TFT panel in a manufacturing stepfollowing the FIGS. 34A to 34C.

FIGS. 35B and 35C are respectively the cross-sectional views taken alongthe line XXXVB-XXXVB′ and XXXVC-XXXVC′ of the FIG. 35A.

FIG. 36 is a layout view of a TFT panel for an LCD according to theeighth embodiment of the present invention.

FIGS. 37 and 38 are cross-sectional views respectively taken along theline XXXVII-XXXVII′ and XXXVIII-XXXVIII′ of the FIG. 36.

FIG. 39A is a layout view of a TFT panel in the first manufacturing stepaccording to the eighth embodiment of the present invention.

FIGS. 39B and 39C are respectively the cross-sectional views taken alongthe line XXXIXB-XXXIXB′ and XXXIXC-XXXIXC′ of the FIG. 39A.

FIG. 40A is a layout view of a TFT panel in a manufacturing stepfollowing the FIGS. 39A to 39C.

FIGS. 40B and 40C are respectively the cross-sectional views taken alongthe line XLB-XLB′ and XLC-XLC′ of the FIG. 40A.

FIG. 41A is a layout view of a TFT panel in a manufacturing stepfollowing the FIGS. 40A to 40C.

FIGS. 41B and 41C are respectively the cross-sectional views taken alongthe line XLIB-XLIB′ and XLIC-XLIC′ of the FIG. 41A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein. In the drawings, the thickness of layersand regions are exaggerated for clarity. Like numerals refer to likeelements throughout. It will be understood that when an element such asa layer, region or substrate is referred to as being “on” anotherelement, it can be directly on the other element or intervening elementsmay also be present. In contrast, when an element is referred to asbeing “directly on” another element, there are no intervening elementspresent

Now, a structure of a TFT array panel according to an embodiment of thepresent invention will be described with reference to the FIGS. 1 to 5.

As shown in FIG. 1, a plurality of panel areas are formed on aninsulating plate 10. For example, as shown in FIG. 1, four panel areas110, 120, 130 and 140 are formed oh a glass plate 10. When the panelsare TFT array panels, the panel areas 110, 120, 130 and 140 includedisplay areas 111, 121, 131 and 141 having a plurality of pixels andperipheral areas 112, 122, 132 and 142, respectively. TFTs, wires andpixel electrodes are repeatedly arranged in a matrix shape in thedisplay areas 111, 121, 131 and 141. Pads to be connected to externalcircuits and electrostatic discharge protection circuits are provided inthe peripheral areas 111, 121, 131 and 141.

In general, the elements in the panel areas 110, 120, 130 and 140 areformed by photolithography using a stepper, an exposure equipment. Whenusing the stepper, the display areas 111, 121, 131 and 141 and theperipheral areas 112,122, 132 and 142 are divided into several sections,and a PR layer coated on thin films is exposed to light section bysection through one or more masks. Then, the PR layer is developed, andthe thin films under the PR layer is etched to form thin film patterns.A complete LCD panel is obtained by repeating the above describedpatterning step.

FIG. 2 is a layout view of a TFT array panel area shown in FIG. 1according to an embodiment of the present invention.

As shown in FIG. 2, a number of TFTs, a plurality of pixel electrodeselectrically connected to the TFTs and a plurality of wires includinggate lines 22 and data lines 62 are formed in the display areasurrounded by an imaginary line 1. Gate pads 24 and data pads 64respectively connected to the gate lines 22 and the data lines 62, and agate shorting bar 4 and a data shorting bar 5 are formed in theperipheral area. The gate shorting bar 4 and the data shorting bar 5connect to the whole gate lines 22 and to the whole data lines 62,respectively. The two shorting bars are electrically connected to eachother through a connector 6 to make them in the same potential, therebyprotecting the device elements from the electrostatic discharge failure.The shorting bars 4 and 5 will be removed by cutting the panel along thecutting line 2. A reference numeral 7 represents contact holes that areformed in insulating layers (not shown) interposed between the connector6 and the shorting bars 4 and 5. The connector 6 is connected to theshorting bars 4 and 5 through the contact holes 7.

FIG. 3 is a layout view of a TFT panel for an LCD according to anembodiment of the present invention, and an enlarged view of a portionmainly including a pixel and pads of the FIG. 2. FIGS. 4 and 5 arecross-sectional views respectively taken along the line IV-IV′ and V-V′of the FIG. 3.

A gate wire of metal or conductive material such as aluminum (Al) oraluminum alloy, molybdenum (Mo) or molybdenum-tungsten (MoW), chromium(Cr) and tantalum (Ta) are formed on an insulating substrate 10. Thegate wire includes a plurality of gate lines (scanning signal lines) 22extending in the horizontal direction, a plurality of gate pads 24 thatare connected to one ends of the respective plurality of gate lines 22and transmit scanning signals from an external circuit to the gate lines22, and a plurality of gate electrodes 26 of TFTs, which are branches ofthe gate lines.

The gate wire 22, 24 and 26 may have a multiple-layered structure aswell as a single-layered structure. When the gate wire 22, 24 and 26 hasformed a multiple-layered structure; it is preferable that one layer ismade of a material having a low resistivity and another layer is made ofa material that has a good contact with other materials. The doublelayers of Cr/Al (or Al alloy) and Al/Mo are such examples.

A gate insulating layer 30 of silicon-nitride (SiNx) is formed on thegate wire 22, 24 and 26 and covers the same. The gate insulating layer30 has a net-shaped pattern.

A semiconductor pattern 42 and 47 made of semiconductor such ashydrogenated amorphous silicon is formed on the gate insulating layer30. The semiconductor pattern 42 and 47 has two portions, a plurality ofthe first portions 42 extend to the vertical direction and a pluralityof the second portions 47 are isolated from the first portion 42 andlocated between two of the first portions 42. The first portion 42adjacent to a gate pad 24 extends to it and forms a branch on the gatepad 24.

An ohmic contact layer pattern 55, 56, 57 and 58 made of amorphoussilicon heavily doped with impurities such as phosphorus is formed onthe semiconductor pattern 42 and 47.

A data wire 62, 64, 66, 67 and 68 made of conductive materials such asMo or MoW, Cr, Al or Al alloy and Ta is formed on the ohmic contactlayer pattern 55, 56, 57 and 58. The data wire 62, 64, 66, 67 and 68 hasa plurality of data lines 62 including a plurality of source electrodes65 of thin film transistors (TFTs) and extending in the verticaldirection, data pads 64 connected to one end of the data lines 62 andtransmitting image signals from an external circuit to the data lines62. The data wire also has a plurality of drain electrodes 66 located atthe opposite side of the source electrodes 65 with respect to the gateelectrodes 26, first isolated data conductors 68 formed on the gate pads24, and second isolated data conductors 67 formed on the second portions47 of the semiconductor layer. The ohmic contact layer pattern 55, 56,57 and 58 is formed between the semiconductor layer pattern 42 and 47and the data wire 62, 64, 66, 67 and 68, and has the same layout as thedata wire 62, 64, 65, 66 and 68.

On the other hand, the gate insulating layer 30, the semiconductor layer42, the ohmic contact layer patterns 58 and the first isolated dataconductors 68 that are located on the gate pads 24 have a plurality ofcontact holes to expose the gate pads 24.

A plurality of conductive pattern 71, 72, 73, 74, 75, 76 and 77 made ofa transparent and conductive material such as ITO (indium tin oxide) isformed on the data wire 62, 64, 66, 67 and 68 and the substrate 10 ofthe pixel regions surrounded by the gate lines 22 and the data lines 62.The conductive pattern 71, 72, 73, 74, 75, 76 and 77 includes aplurality of first patterns to fourth patterns. The first pattern 72 and75 formed on the data line 62 and the data pad 64 is classified into twoportions, one is a portion 75 on the source electrode 65 and the otheris elsewhere 72. The second pattern 71 and 76 includes a plurality ofportions 76 on the drain electrode 66 and a plurality of pixelelectrodes 71 in the pixel areas. As shown in FIG. 3, The pixelelectrode 71 extends to and is formed on the second isolated dataconductor 67 to form a storage capacitor by overlapping with theprevious gate line 22. The third pattern 74 is formed on the data pad 64to assist ohmic contact between the data pad 64 and a external circuit,and the fourth pattern 73 is formed on the gate pad 24 exposed throughthe contact hole to assist an ohmic contact between the gate pad 24 andan external circuit. At this time, the first pattern 72 and 75 isconnected with the third pattern 74, while the second and the fourthpattern 71, 73 and 76 are separated from the first pattern 72, 74 and75. The fourth pattern 73 may be omitted.

In this embodiment, the conductive pattern is made of a transparentmaterial, but it can be made of an opaque material in a reflective typeLCD.

A passivation layer 80 made of insulating material such as SiNx isformed on the described structure, and has a plurality of openings 83,84 and 85 respectively exposing the pixel electrode 71 and the third andthe fourth pattern 73 and 74 of transparent conductor and openings 81and 82 exposing the gate insulating layer 30. The openings 81 and 82separate the semiconductor layer into two portions 42 and 47. It is toprevent a parasitic transistor of the gate line 22 as a gate, the dateline 62 as a source and the pixel electrode 71 as a drain from beingformed, as shown in FIG. 5. Since, in a previous gate type LCD like thepresent embodiment, where the pixel electrode 71 is overlapped with theprevious gate line, such a parasitic transistor can cause a big problem.On the other hand, the semiconductor layer may form an electricalchannel when voltages applied. The two adjacent data lines connected viaa semiconductor layer may interfere the signals of the two data lineswith each other. Therefore, the semiconductor layer needs to beseparated in other types of LCDs as well as in the previous gate typeLCD. An embodiment, which is not a previous gate type LCD will bedescribed in the fourth embodiment of the present embodiment.

Now, a manufacturing method of a thin film transistor array panelaccording to the first embodiment of the present invention will bedescribed with reference to the FIGS. 6A to 8C and FIGS. 3 to 5mentioned above.

FIGS. 6A, 7A and 8A are layout views of a TFT panel and are sequentiallyarranged according to the manufacturing step of the first embodiment ofthe present invention. FIGS. 6B, 6C, 7B, 7C, 8B and 8C are respectivelythe cross-sectional views taken along the line VIB-VIB′ and VIC-VIC′ ofthe FIG. 6A, VIIB-VIIB′ and VIIC-VIIC′ of the FIG. 7A and VIIIB-VIIIB′and VIIIC-VIIIC′ of the FIG. 8A.

At first, as shown in FIGS. 6A to 6C, a conductor layer is deposited ona substrate 10 by such methods as sputtering to have a thickness 1,000Åto 3,000 Å, and a gate wire including a gate line 22, a gate pad 24 anda gate electrode 26 is formed by dry etch or wet etch using the firstmask. As described above, the gate wire 22, 24 and 26 may be formed ofdouble layers of Al—Nd and Mo—W, in which case the dry etch ispreferable . When the gate wire is formed of double layers of Cr andAl—Nd, the wet etch is preferable.

Next, as shown in FIGS. 7A to 7C, a gate insulating layer 30, asemiconductor layer 40, an ohmic contact layer 50 and a data conductorlayer 60 of Cr or Al—Nd alloy are sequentially deposited and patternedby dry etch. At this time, as shown in FIG. 7A, the pattern of the fourlayer 30, 40, 50 and 60 is formed to have a mesh type, covering thewhole gate wire 22, 24 and 26. The pixel area has an opening 220exposing the substrate 10, and a contact hole 210 is formed to exposethe gate pad 24.

Next, as shown in FIG. 8A to 3C, an ITO layer is deposited and patternedby using the third mask and dry etch to form a conductive pattern 71,72, 73; 74, 75, 76 and 77. Then, the portion not covered by thetransparent conductor layer of the data conductor layer 60 and the ohmiccontact layer 50 is etched by dry etch.

Next, as shown in FIG. 3 to 5, a passivation layer 80 of SiNx isdeposited and patterned by using the fourth mask to form the openings81, 82, 83, 84 and 85, and the semiconductor layer 40 exposed throughthe openings 81 and 82 is etched to divide it into two pieces 42 and 47.At this time, the etch processes of the passivation layer 80 and thesemiconductor layer 40 may be performed in sequence by using a dry etch.A mixture of chlorine gas (Cl₂) and oxygen gas (O₂), of which etch ratiofor the SiNx with respect to the amorphous silicon is about 10:1, may beused as an etch gas.

Such a thin film transistor panel may be manufactured by varieties ofdifferent ways to have varieties of different structures.

A TFT array panel and a manufacturing method thereof according to asecond embodiment of the present invention will be described.

FIG. 9 is a layout view of a TFT panel for an LCD according to thesecond embodiment of the present invention and an enlarged view of aportion mainly including a pixel and pads of the FIG. 2, and FIGS. 10and 11 are cross-sectional views respectively taken along the line X-X′and XI-XI′ of the FIG. 9.

As shown in FIGS. 9 to 11, the structure of the TFT array panel of thesecond embodiment is almost the same as that of the first embodimentexcept for that around the pads. That is to say, between the pads, thegate insulating layer 30 is removed in the first embodiment, but is notremoved in the second embodiment. In addition, in the second embodiment,the passivation layer 80 has an opening 86 marked as slanted creases,exposing the gate insulating layer 30 between the pads. Therefore, thepads are not connected to each other through the semiconductor layer.

Now, a manufacturing method of a thin film transistor array panelaccording to the second embodiment of the present invention will bedescribed with reference to the FIGS. 12A to 13B and FIGS. 9 to 11mentioned above.

FIGS. 12A and 13A are layout views of a TFT panel and are sequentiallyarranged according to the manufacturing step of the second embodiment ofthe present invention, FIGS. 12B and 13B are respectively thecross-sectional views taken along the line XIIB-XIIB′ of the FIG. 12Aand XIIIB-XIIIB′ of the FIG. 13A.

At first, like the first embodiment, a gate wire 22, 24 and 26 isformed. Then, four layers of a gate insulating layer 30, a semiconductorlayer 40, an ohmic contact layer 50 and a data conductor layer 60 aresequentially deposited and patterned . At this time, as shown in FIG.12A and 12B, the four layers around pads are not removed.

Next, as shown in FIGS. 13A and 13B, an ITO layer is deposited andpatterned by using the third mask and dry etch to form a conductivepattern 71, 72, 73, 74, 75, 76 and 77. Then, the portion not covered bythe transparent conductor layer of the data conductor layer 60 and theohmic contact layer 50 is etched by dry etch.

Next, as shown in FIGS. 9 to 12, a passivation layer 80 is deposited andpatterned by using the fourth mask to form the openings 81, 82, 83, 84and 85. Then, the semiconductor layer 40 exposed through the openings81, 82 and 86 is etched to separate the portions of the semiconductorlayer 40 under the data lines from each other and remove the portionbetween the pads.

In the first and the second embodiment, the edge of the pixel electrode71 is covered by the passivation layer 80, but it may not be covered bythe passivation layer 80. This case will be described by the thirdembodiment with reference to the FIGS. 14 and 15. FIG. 15 is across-sectional view taken along the line XV-XV′ of the FIG. 14.

As shown in FIGS. 14 and 15, an opening 85 of a passivation layer 80exposes the edge of a pixel electrode 71. Therefore, the portion of asubstrate 10 between the passivation 80 and the pixel electrode 71 isexposed. The other structure is almost the same as that of the firstembodiment.

Such a structure is necessary for preventing the pixel electrode 71 fromshortening with the data line 62 or the conductive pattern 72 on thedata line 62 through the semiconductor layer 42. That is to say,although the pixel electrode 71 is formed on the semiconductor layer 42,which is under the data line 62 but both sides of which is not coveredby the data line 62 by misalignment, the exposed portion of thesemiconductor layer 42 through the opening 85 is removed by etch afterforming the opening 85. Therefore, the portion of semiconductor layerunder the pixel electrode 71 is separated from the portion under thedata line 62.

The first through the third embodiments are about the previous gate typeTFT array panel, but the present invention may also be applied to aseparated common line type TFT array panel. This will be described inthe fourth embodiment.

FIG. 16 is a layout view of a TFT panel for an LCD according to thefourth embodiment of the present invention. FIGS. 17 and 18 arecross-sectional views respectively taken along the line XVII-XVII′,XVIII-XVIII′ of the FIG. 16.

As shown in FIGS. 16 to 18, a storage wire 27 and 28 is formed on aninsulating substrate 10 along with a gate wire 22, 24 and. 26. Thestorage wire 27 and 28 is made of the same material and is on the samelayer with the gate wire 22, 24 and 26. The gate wire includes a gateline (scanning signal line) 22 extending in the horizontal direction, agate pad 24 connected to an end of the gate line 22 and transmitting ascanning signal from an external circuit to the gate line 22, and a gateelectrode 26 that is a part of thin film transistor. The storage wireincludes a storage line 27, which is separated from and laid in parallelwith the gate line 22, extending to a horizontal direction, and astorage pad 28 connected to the end of the storage line 27.

A gate insulating layer 30 is formed on the gate wire 22, 24 and 26 andthe storage wire 27 and 28, and a semiconductor layer 42 and 49 isformed on the gate insulating layer 30.

The semiconductor pattern has two portions, 42 and 49. The first portion42 is extending to a vertical direction and the second portion 49 islocated between the two first portion 42 and on the storage line 27. Thesecond portion 49 is isolated from the first portion 42.

An ohmic contact layer 55, 56, 58 and 59 is formed on the semiconductorpattern 42 and 49, and a data wire 62, 64, 66, 68 and 69 made ofconductive materials such as Mo or MoW, Cr and Ta is formed on the ohmiccontact layer pattern 55, 56, 58 and 59. The data wire has a data line62 including a source electrode 65 and extending in the verticaldirection, a data pad 64 connected to an end of data line 62, a drainelectrode 66, a first isolated data conductor 68, and a second isolateddata conductor 69 formed on the second portion 49 of the semiconductorlayer. The ohmic contact layer pattern 55, 56, 58 and 59 is formedbetween the semiconductor layer 42 and 49 and the data wire 62, 64, 66,68 and 69, and has the same layout as the data wire 62, 64, 65, 68 and69.

On the other hand, the gate insulating layer 30, the semiconductor layer42, the ohmic contact layer 58 and the first isolated data conductor 68that are located on the gate pad 24 and the storage pad 28 have acontact hole to expose the gate pad 24 and the storage pad 28.

A conductive pattern 71, 72, 73, 74, 75, 76 and 77 made of a transparentand conductive material such as ITO (indium tin oxide) is formed on thedata wire 62, 64, 66, 68 and 69 and the substrate 10 of pixel area,which is defined as an area surrounded by the gate line 22 and the dataline 62. The conductive pattern 71, 72, 73, 74, 75, 76 and 77 includes afirst pattern through a fourth pattern. The first pattern formed on thedata line 62 and the data pad 64 is classified into a portion 75 on thesource electrode 65 and elsewhere 72. The second pattern includes aportion 76 on the drain electrode 66 and a pixel electrode 71 on thepixel area. As shown in FIG. 16, The pixel electrode 71 is elongated toand formed on the second isolated data conductor 69 to form a storagecapacitor by overlapping with the storage line 27. The third pattern 74is formed on the data pad 64 to enhance the ohmic contact between thedata pad 64 and an external circuit, and the fourth pattern 73 is formedon the gate pad 24 and the storage pad 28 exposed through the contacthole to enhance the ohmic contact between the gate pad 24 and anexternal circuit as well as the storage pad 28 and an external circuit.

A passivation layer 80 made of insulating material such as SiNx isformed on the described structure. The passivation layer 80 has anopening that exposes the pixel electrode 71 and the portion of the gateinsulating layer 30 between the two adjacent data lines. As a result,the passivation layer 80 is formed along the data line 62. This openingis formed to remove the portion of the semiconductor layer 42 exposedthrough the opening, therefore, to prevent the two adjacent data line 62from shortening to each other. At the same time, the pixel electrode 71is exposed. The passivation layer 80 also has openings 83 and 84respectively exposing the third and the fourth transparent conductivepattern 73 and 74.

The other structure is similar to the third embodiment.

The manufacturing method according to the fourth embodiment is almostthe same as that of the first embodiment except that the storage wire 27and 28 is formed along with the gate wire 22, 24 and 26.

Now, the fifth embodiment that applies the present invention to a ringgate type TFT array panel will be described.

FIG. 19 is a layout view of a TFT panel for an LCD according to thefifth embodiment of the present invention, FIG. 20 is a cross-sectionalview taken along the line XX-XX′ of the FIG. 19.

As shown in FIGS. 19 and 20, a gate wire 22, 25 and 26 extending to thehorizontal direction is formed on an insulating substrate 10. The gateline 22 comprises a pair of lines, which are connected to each otherthrough a gate line bridge 25. One of the line has a gate electrode.Though not shown in the FIGS. 19 and 20, a gate pad is formed at an endof the gate line 22 in the same way as the former embodiment.

A gate insulating layer 30 is formed on the gate wire 22, 25 and 26, anda semiconductor layer 42 is formed on the gate insulating layer 30. Thesemiconductor layer 42 has a first portion, which is extended to avertical direction, and a second portion, which is separated from thefirst portion except for the channel part of TFT and overlapped with apart of the gate line 22 and the gate line bridge 25.

An ohmic contact layer 55, 56 and 57 is formed on the semiconductorlayer 42, and a data wire 62, 65, 66 and 67 is formed on the ohmiccontact layer 55, 56 and 57. The data wire 62, 65, 66 and 67 includes adata line 62, a source electrode 65 connected to the data line 62 andhaving a “U” shape concave part, a drain electrode 66 formed in theconcave part of the source electrode 65, and a storage electrode 67 thatis connected to the drain electrode 66 and overlapped with the secondportion of the semiconductor layer 42. Though not shown in the FIGS. 19and 20, a data pad is formed at an end of the data line 22 and anisolated data conductor is formed on the gate pad in the same manner asthe former embodiment. The ohmic contact layer pattern 55, 56 and 57 isformed between the semiconductor layer 42 and the data wire 62, 65, 66and 67, and has the same layout as the data wire 62, 65, 66 and 67.

On the other hand, the gate insulating layer 30, the semiconductor layer42, the ohmic contact layer and the isolated data conductor that arelocated on the gate pad 24 have a contact hole to expose the gate pad24.

A conductive pattern 71, 72, 75 and 76 made of a transparent andconductive material such as ITO (indium tin oxide) is formed on the datawire 62, 65, 66 and 67 and the substrate 10 of pixel area defined by thegate line 22 and the data line 62. At this time, the transparentconductive pattern 72, 75 and 76 has the same layout as the data wire62, 65, 66 and 67 thereunder, except for the pixel electrode 71 and theportion of the transparent conductive pattern on the gate pad and thedata pad. It is because the data wire 62, 65, 66 and 67 and the ohmiccontact layer 55, 56 and 57 are patterned by using the transparentconductive pattern 72, 75 and 76 as etch mask. The pixel electrode 71 iselongated to and formed on the storage electrode 67, and overlapped withthe gate line 22 and the gate line bridge 25 to form a storagecapacitor. Like the former embodiment, the transparent conductivepatterns on the gate pad and the data pad enhance the ohmic contactbetween the gate pad, the data pad and the external circuit.

A passivation layer 80 of insulating material such as SiNx is formed onthe above-mentioned structure. The passivation layer 80 has an opening85 exposing the pixel electrode 71 and a trench 81 that is exposing thegate insulating layer 30 and the substrate 10 and is formed along theedge of the pixel electrode 71. At this time, the trench 81 is extendedto the vertical direction, and surrounds the pixel electrode 71 exceptfor the portion connected to the drain electrode 66. The trench 81 isformed to prevent the two adjacent data line 62, and the pixel electrode71 and the data line 62 from shortening to each other through thesemiconductor layer 42 or ITO residue by removing the semiconductorlayer 42 and ITO residue under the trench 81.

The manufacturing method of the fifth embodiment is the same as that ofthe first to the fourth embodiment in other aspects.

Other methods to achieve the object of the present invention will bedescribed by the sixth through the eighth embodiments.

The structure of TFT array panel according to the sixth embodiment willbe described with reference to the FIG. 21 and 22. FIG. 21 is a layoutview of a TFT panel for an LCD according to the sixth embodiment of thepresent invention. FIG. 22 is a cross-sectional view taken along theline XXII-XXII′ of the FIG. 21.

At first, gate wires of metal or conductive material such as aluminum(Al) or aluminum alloy, molybdenum (Mo) or molybdenum-tungsten (MoW),chromium (Cr) and tantalum (Ta) are formed on an insulating substrate10. A gate wire includes a gate line (scanning signal line) 22 extendingin the horizontal direction, a gate pad 24 formed at the end of the gateline 22 and transmitting a scanning signal from an external circuit tothe gate line 22, and a gate electrode 26 that is a part of thin filmtransistor.

The gate wire 22, 24 and 26 may have a multiple-layered structure aswell as a single-layered structure. When the gate wire 22, 24 and 26 hasformed a multiple-layered structure, it is preferable that one layer ismade of a material having a low resistivity and another layer is made ofa material having a good contact with other materials. The double layersof Cr/Al (or Al alloy) and Al/Mo are such examples.

A gate insulating layer 30 of silicon-nitride (SiNx) is formed on thegate wire 22, 24 and 26, covering them. The gate insulating layer 30covers the substrate 10 of the display area but does not cover the gatepad 24 and the substrate 10 of the peripheral area.

A semiconductor pattern 42 of such as hydrogenated amorphous silicon 20is formed on the gate insulating layer 30. An ohmic contact layerpattern 55 and 56 of amorphous silicon heavily doped with impuritiessuch as phosphorus is formed on the semiconductor pattern 42.

A data wire 62, 64, 65 and 66 made of conductive materials such as Mo orMoW, Cr, Al or Al alloy, and Ta is formed on the ohmic contact layerpattern 55 and 56. The data wire has a data line 62 including a sourceelectrode 65 and extending in the vertical direction, a data pad 64connected to an end of data line 62 and transmitting image signals froman external circuit to the data line 62. The data wire also has a drainelectrode 66 located at the opposite side of the source electrode 65with respect to the gate electrode 22.

The data wire 62, 64, 65 and 66 may have a multiple-layered structurelike the gate wire 22, 24 and 26. Of course, when the data wire has amultiple-layered structure, it is preferable that one layer is made of amaterial having a low resistivity and another is made of a materialhaving a good contact with other materials.

The ohmic contact layer pattern 55 and 56 plays a role of reducing thecontact resistance between the semiconductor pattern 42 and the datawire 62, 64, 65 and 66, having the same layout as the data wire 62, 64,65 and 66. The semiconductor pattern 42 has the same layout as the datawire 62, 64, 65 and 66 and the ohmic contact layer pattern 55 and 56except for the channel part between the source electrode 65 and thedrain electrode 66.

A conductive pattern 71, 72, 73 and 74 made of a transparent andconductive material such as ITO (indium tin oxide) is formed on the datawire 62, 64, 65 and 66. The conductive pattern includes a pixelelectrode 71 formed on the substrate 10 of the pixel area, surrounded bythe gate line 22 and the data line 62. The pixel electrode 71 isextended to the drain electrode 66 and formed on it, overlapping thegate line 22 to make a storage capacitor. The conductive pattern 71, 72,73 and 74 also includes a redundant data line, a redundant data pad anda redundant gate pad that respectively covers the data line, the datapad and the gate pad.

In the sixth embodiment, a passivation layer 80 covers the conductivepattern 72, 73, and 74 except for the pixel electrode 71, thesemiconductor layer pattern 42 that is not covered by the conductivepattern 71, 72, 73 and 74, the redundant gate pad 73, and the gate wire22, 24 and 26 that is not covered by the gate insulating layer 30.However, the passivation layer 80 may be formed to cover only thechannel of the TFT that is a part of the semiconductor layer pattern 42between the source electrode 65 and the drain electrode 66. Thepassivation layer 80 may be made of SiNx or an organic insulator such asan acrylic resin.

In this embodiment, the conductive pattern is made of a transparentmaterial, but it can be made of an opaque material in a reflective typeLCD.

Now, a method for manufacturing a thin film transistor array panelaccording to the sixth embodiment of the present invention will bedescribed with reference to the FIGS. 23A to 29B and FIGS. 21 and 22mentioned above.

At first, as shown in FIGS. 23A and 23B, a layer of conductor such as ametal is deposited on a substrate 10 by such a method as sputtering to athickness 1,000 Å to 3,000 Å. A gate wire including a gate line 22, agate pad 24 and a gate electrode 26 is formed by dry etch or wet etchusing the first mask.

Next, as shown in FIGS. 24A and 24B, a gate insulating layer 30, asemiconductor layer 40 and an ohmic contact layer 50 are sequentiallydeposited to have the thickness of 1,500 Å to 5,000 Å, 500 Å to 2,000 Åand 300 Å to 600 Å respectively by such a method as chemical vapordeposition (CVD). Then, a metal layer 60 is deposited to have thethickness of 1,500 Å to 3,000 Å by such a method as sputtering. Themetal layer 60, the ohmic contact layer 50, the semiconductor layer 40and the gate insulating layer 30 are patterned to form a metal layerpattern 61, a first ohmic contact layer pattern 51 and a semiconductorlayer pattern 42 thereunder, as shown in FIG. 28. At this time, themetal layer pattern 61 is similar to the completed data wire except thata source electrode and the drain electrode are not separated yet. In theperipheral area P, the metal layer 70, the ohmic contact layer 50, thesemiconductor layer 40 and the gate insulating layer 30 except for themetal layer pattern 61 and the underlying layers are removed. However,in the display area D, the gate insulating layer 30 remains as well asthe metal layer pattern 61 and the underlying layers. For this purpose,a photoresist (PR) pattern is formed to have a thickness that variesdepending on the location. The layers under the PR pattern are dryetched using the PR pattern as an etch mask. It will be described withreference to the FIGS. 24B to 27.

At first, a PR layer, preferably positive, is coated to a thickness of5,000 Å to 30,000 Å on the metal layer 60, and exposed to light throughthe third mask 300, 410 and 420. As shown in the FIG. 24B, the PR layerin the display area D are different from that in the peripheral area P.In concrete, in the display area D, polymers in exposed portion C arepartly resolved from the surface to a certain depth, remaining thepolymer below the depth intact. However, in the peripheral area P,polymers in exposed portion B are entirely resolved from the surface tothe bottom. At this time, the metal layer 60 under the exposed portionsC and B is subject to being removed.

For this purpose, a mask 300 that will be aligned on the display area Dmay have a different structure from masks 410 and 420 that will bealigned on the peripheral area P. Three of such methods will bedescribed.

At first, as shown in FIGS. 25A and 25B, masks 300 and 400 includenormal substrates 310 and 410, opaque pattern layer 320 and 420 of suchas Cr thereon, and pellicles 330 and 430 covering the opaque patternlayer 320 and 420 and the exposed substrates 310 and 410. The lighttransmittance of pellicle 330 on the mask 300 for the display area D islower than that of the pellicle 430 on the mask 400 for the peripheralarea P. It is preferable that the light transmittance of pellicle 330 is10% to 80%, more preferably 20% to 60%, of the light transmittance ofpellicle 430.

Next, as shown in FIGS. 26A and 26B, a Cr layer 350 remains to athickness of 100 Å to 300 Å on the entire mask 300 for the display areaD to reduce the light transmittance, and the mask 400 for the peripheralarea P does not have the Cr layer 35 remaining. At this time, the lighttransmittance of the pellicle 340 for the mask 300 may be equal to thatof the pellicle 430.

A mixed way of above two methods may be available.

Above two methods are available for a multi-shot exposure using astepper, since the mask for the display area D and that of theperipheral area P may be different pieces. At this time, the thicknessof the PR layer may be controlled by adjusting the exposure time.

However, the display area D and the peripheral area P may be exposed tolight through one mask. A mask for this method will be described withreference to the FIG. 27.

As shown in FIG. 27, a transmittance controllable layer 550 is formed ona substrate 510 for 500, and a pattern layer 520 is formed on thetransmittance controllable layer 550. The transmittance controllablelayer 550 is formed not only under the pattern layer 520 but also on thewhole area that is going to be aligned on the display area D, but onlyunder the pattern layer 520 on the area that is going to be aligned onthe peripheral area P. As a result, at least two patterns having athickness different from each other are formed on the substrate 510.

A transmittance controllable layer may be formed on the area aligned onthe peripheral area P. At this time, the transmittance of thetransmittance controllable layer for the peripheral area P should behigher than that of the transmittance controllable layer for the displayarea D.

To manufacture such a photomask 500 having a transmittance controllablelayer 550, the transmittance controllable layer 550 and a pattern layer520 that has an etch ratio different from the transmittance controllablelayer 550 are sequentially piled up on the substrate 500. A PR layer(not shown) is coated on the whole substrate 500, exposed to light anddeveloped. Then the pattern layer 520 is etched to obtain the completedphotomask 500 by using the PR layer as etch mask.

In other way, the light transmittance may be controlled by using a maskthat has a slit or a lattice pattern smaller than the resolution ofexposing light.

The PR layer is exposed and developed to form a PR pattern havingdifferent thickness depending on the location, as shown in FIG. 25B. Inconcrete, there is no PR layer on the peripheral area except for wherethe metal layer pattern 61 will be formed. A thick PR layer A is formedon which the metal layer pattern 61 will be formed. A thin PR layer C isformed elsewhere of the display area D.

At this time, it is preferable that the thickness of the thin PR layer Cis ¼ to 1/7 of the original thickness, in other words 350 Å to 10,000 Å,and more preferably 1,000 Å to 6,000 Å. For example, when the originalthickness of the PR layer is 16,000 Å to 24,000 Å, a thin PR layerhaving a thickness of 3,000 Å to 7,000 Å may be obtained by setting thetransmittance to 30%. Since the thickness of the PR layer should bedecided depending on the dry etch condition, the pellicle and thethickness of the remaining Cr layer, the transmittance of thetransmittance controllable layer and the exposure time should becontrolled depending on the etch condition.

The thin PR layer may be formed by reflow. At this time, a normalexposure and a normal development may be used:

Then, the PR pattern and the underlying layers, in other words, themetal layer 60, the ohmic contact layer 50, the semiconductor layer 40and the gate insulating layer 30 are dry etched.

At this time, as mentioned above, portion A of the PR pattern shouldremain, and the metal layer 60, the ohmic contact layer 50, thesemiconductor layer 40 and the gate insulating layer 30 under portion Bshould be removed. The metal layer 60, the ohmic contact layer 50 andthe semiconductor layer 40 under portion C should be removed but thegate insulating layer 30 under the C portion should remain.

To achieve this structure, the exposed metal layer 60 of peripheral areais removed to expose the ohmic contact layer 50 by dry etch or wet etch.Next, the PR layer and the underlying layers are etched by a dry etch.The PR layer, the ohmic contact layer 50 and the semiconductor layer 40can be etched at a time. At this time, it is etched until the thin PRlayer C is wholly removed and the underlying metal layer 60 is exposed.At this time, the exposed ohmic contact layer 50 and the underlyingsemiconductor layer 40 are also etched. By the etch, the semiconductorlayer 40 may remain to a certain thickness or wholly removed to exposethe gate insulating layer 30. The gate insulating layer 30 may also beetched to some extent, depending on the etch condition and the thicknessof the layers 40 and 50. At this time, the thick PR layer A is alsoetched to some extent. Next, the exposed metal layer 60 under portion Cis removed to expose the ohmic contact layer 50 by dry etch or wet etch.The ohmic contact layer and the underlying layers are etched by dryetch. The ohmic contact layer 50, the semiconductor layer 40 and thegate insulating layer 30 can be etched at a time. It is etched until thegate pad 24 is exposed. At this time, the ohmic contact layer 50 and thesemiconductor layer 40 under portion C are removed.

Therefore, the metal layer pattern 61, the first ohmic contact layerpattern 51 and the semiconductor layer pattern 42 of the display area isformed, and the metal layer 60, the ohmic contact layer 50, thesemiconductor layer 40 and the gate insulating layer 30 of theperipheral area except for the metal layer pattern 61 is removed, by onephotolithography step.

Next, after the remaining PR is removed, an ITO layer is deposited tohave a thickness of 400 Å to 500 Å by such a method as sputtering. Then,the ITO layer is patterned to form the conductive pattern 71, 72, 73 and74 as shown in FIGS. 29A and 29B. At this time, the portion between thepixel electrode 71 and the redundant data line 72 of the metal layerpattern 61 is exposed. The exposed metal layer pattern 61 is wet etchedto separate the source electrode 65 from the drain electrode 66,exposing the first ohmic contact layer pattern 51 thereunder. Then theexposed first contact pattern 51 is etched out to expose thesemiconductor layer 42, achieving a complete TFT.

As a last step, a passivation layer 80 of over 3,000 Å is formed by CVD(chemical vapor deposition) of SiNx or spin coating an organicinsulating layer and patterned using the fourth mask. At this time, thepassivation layer 80 may be made of a photo-definable material. In thiscase, the passivation layer 80 may be patterned only by exposure anddevelopment without laying a photoresist layer. This step of patterningexposes the pixel electrode 71, the redundant gate pad 73 and theredundant data pad 74.

As described above, the number of photolithography step is reduced bypatterning at the same time the gate insulating layer 30 covering thegate pad 24 along with the metal layer pattern 61, the first ohmiccontact layer pattern 51 and the semiconductor layer pattern 42.

In the sixth embodiment, the TFT array panel has pixel electrodes only.But the present invention may also be applied to the TFT array panelhaving common electrodes as well as pixel electrodes. It will bedescribed by the seventh embodiment with reference to FIGS. 30 to 35C.

At first, the structure of the TFT array panel according to the seventhembodiment will be described.

FIG. 30 is a layout view of a TFT panel for an LCD according to theseventh embodiment of the present invention, FIGS. 31 and 32 arecross-sectional views respectively taken along the line XXXI-XXXI′ andXXXII-XXXII′ of the FIG. 30.

At first, a gate wire of metal or conductive material such as aluminum(Al) or aluminum alloy, molybdenum (Mo) or molybdenum-tungsten (MoW),chromium (Cr) and tantalum (Ta) is formed on an insulating substrate 10.A gate wire includes a gate line (scanning signal line) 22 extending inthe horizontal direction, a gate pad 24 connected to an end of the gateline 22 and transmitting a scanning signal from an external circuit tothe gate line 22, and a gate electrode 26 that is a part of thin filmtransistor.

A common electrode wire made of the same material as the gate wire isalso formed on the substrate 10. The common electrode wire includes acommon line 27, common electrodes 28 that is a vertical branch of thecommon line 27 and a common pad (not shown) connected to an end of thecommon line 27 and transmitting a common electrode signal from anexternal circuit to the common line 27. The common pad is very similarto the gate pad 24.

A gate insulating layer 30 of silicon-nitride (SiNx) is formed on thegate wire 22, 24 and 26 and the common electrode wire 27 and 28, andcovers them. The gate insulating layer 30 covers the substrate 10 of thedisplay area but do not cover the gate pad 24, the common pad and thesubstrate 10 of the peripheral area.

A semiconductor pattern 42 made of semiconductor such as hydrogenatedamorphous silicon is formed on the gate insulating layer 30. An ohmiccontact layer pattern 55 and 56 made of amorphous silicon heavily dopedwith impurities such as phosphorus is formed on the semiconductorpattern 42.

A data wire 62, 64, 65 and 66 made of conductive materials such as Mo orMoW, Cr, Al or Al alloy and Ta is formed on the ohmic contact layerpattern 55 and 56. The data wire has a data line 62 including a sourceelectrode 65 and extending in the vertical direction, a data pad 64connected to an end of data line 62 and transmitting image signal froman external circuit to the data line 62. The data wire also has a drainelectrode 66 located at the opposite side of the source electrode 65with respect to the gate electrode 22.

The ohmic contact layer pattern 55 and 56 plays a role to reduce thecontact resistance between the semiconductor pattern 42 and the datawire 62, 64, 65 and 66, and has the same layout as the data wire 62, 64,65 and 66. The semiconductor pattern 42 has the same layout as the datawire 62, 64, 65 and 66 and the ohmic contact layer pattern 55 and 56except for the channel part between the source electrode 65 and thedrain electrode and 66.

A conductive pattern 72, 73, 74, 75 and 76 made of a transparent andconductive material such as ITO (indium tin oxide) is formed on the datawire 62, 64, 65 and 66. The conductive pattern includes a pixelelectrode line 75 formed on the drain electrode 66 and parallel with thecommon line 27, and pixel electrodes 76 connected to the pixel electrodeline 75 and parallel with the common electrode. The pixel electrode 76and the common electrode 27 are located by turns and generate electricfields between them when voltages applied. The pixel electrode 76 may beoverlapped with the common electrode line 27 to make a storagecapacitor. The conductive pattern also includes a redundant data line 72covering the data line 62 and the source electrode 65, a redundant: datapad 74 covering the data pad 64, a redundant gate pad 73 covering thegate pad 24 and a redundant common pad (not shown) covering the commonpad.

Next, a passivation layer 80 having contact holes 83 and 84 respectivelyexposing the redundant gate pad 73, the redundant data pad 74 and theredundant common pad is formed on the conductive pattern 71, 72, 73 and74. The passivation layer 80 may be made of SiNx or an organic insulatorsuch as an acrylic resin.

Now, a manufacturing method of a thin film transistor array panelaccording to the seventh embodiment of the present invention will bedescribed with reference to the FIGS. 33A to 35C and FIGS. 30 to 32mentioned above.

At first, as shown in FIGS. 33A through 33C, a layer of conductor suchas a metal is deposited on a substrate 10 by such a-method as sputteringto a thickness 1,000 Å to 3,000 Å. A gate wire including a gate line 22,a gate pad 24 and a gate electrode 26 and a common electrode wireincluding a common line 27, common electrodes 28 and a common pad areformed by dry etch or wet etch using the first mask.

Next, as shown in FIGS. 34A through 34C, a gate insulating layer 30, asemiconductor layer 40 and an ohmic contact layer 50 are sequentiallydeposited to have the thickness of 1,500 Å to 5,000 Å, 500 Å to 2,000 Åand 300 Å to 600 Å respectively by such a method as chemical vapordeposition (CVD). Then, a metal layer 60 is deposited to have athickness of 1,500 Å to 3,000 Å by such a method as sputtering. Themetal layer 60, the ohmic contact layer 50, the semiconductor layer 40and the gate insulating layer 30 are patterned to form a metal layerpattern 61, a first ohmic contact layer pattern 51 and a semiconductorlayer pattern 42 thereunder, as shown in FIGS. 34B and 34C. At thistime, the metal layer pattern 61 is similar to the completed data wireexcept that a source electrode and the drain electrode are notseparated. In the peripheral area P, except for the metal layer pattern61, the metal layer 70, the ohmic contact layer 50, the semiconductorlayer 40 and the gate insulating layer 30 and the underlying layers areremoved. However, in the display area, neither the gate insulating layer30 nor the metal layer pattern 61 with the underlying layers areremoved.

It is done by the method described in the sixth embodiment. That is, aPR pattern of which thickness varies depending on the location is formedand etched with the underlying layers at a time.

Next, a conductor layer is deposited to have a thickness of 400 Å to 500Å by such a method as sputtering. Then, the conductor layer is patternedto form the conductive pattern 72, 73, 74, 75 and 76 as shown in FIGS.35A and 35B. At this time, the portion between the pixel electrode line75 and the redundant data line 72 of the metal layer pattern 61 isexposed. The exposed metal layer pattern 61 is wet etched to separatethe source electrode 65 from the drain electrode 66, exposing the firstohmic contact layer pattern 51 thereunder. Then the exposed firstcontact pattern 51 is etched to expose the semiconductor layer 42,achieving a complete TFT.

As a last step, a passivation layer 80 of over 3,000 Å is formed by CVD(chemical vapor deposition) of SiNx or spin coating an organicinsulating layer and patterned by using the fourth mask. This patterningexposes the redundant gate pad 73 and the redundant data pad 74.

Another manufacturing method of TFT array panel using only four steps ofphotolithography process will be described by the eighth embodiment. Inthe eighth embodiment, the common electrode and the pixel electrode areformed on the TFT array panel.

Now, a TFT array panel and a manufacturing method thereof according tothe eighth embodiment of the present invention will be described Withreference to the FIGS. 36 to 41C.

At first, FIG. 36 is a layout view of a TFT panel for an LCD accordingto the eighth embodiment of the present invention. FIGS. 37 and 38 arecross-sectional views respectively taken along the line XXXVII-XXXVII′and XXXVIII-XXXVIII′ of the FIG. 36.

A gate wire of metal or conductive material such as aluminum (Al) oraluminum alloy, molybdenum (Mo) or molybdenum-tungsten (MoW), chromium(Cr) and tantalum (Ta) is formed on an insulating substrate 10. A gatewire includes a gate line (scanning signal line) 22 extending in thehorizontal direction, a gate pad 24 connected to an end of the gate line22 and transmitting a scanning signal from an external circuit to thegate line 22, a gate electrode 26 that is a portion of the gate line 22.

A common electrode wire made of the same material as the gate wire isalso formed on the substrate 10. The common electrode wire includes acommon line 27, common electrodes 28 that is a vertical branch of thecommon line 27 and a common pad (not shown) connected to an end of thecommon line 27 and transmitting a common electrode signal from anexternal circuit to the common line 27. The common pad is very similarto the gate pad 24.

A gate insulating layer 30 of silicon-nitride (SiNx) is formed on thegate wire 22, 24 and 26 and the common electrode wire 27 and 28,covering the same. The gate insulating layer 30 covers the substrate 10of the display area but do not cover the gate pad 24, the common pad andthe substrate 10 of the peripheral area.

A semiconductor pattern 42 made of semiconductor such as hydrogenatedamorphous silicon is formed on the gate insulating layer 30. An ohmiccontact layer pattern 55 and 56 made of amorphous silicon heavily dopedwith impurities such as phosphorus is formed on the semiconductorpattern 42.

A data wire 62, 64, 65, 66, 68 and 69 made of conductive materials suchas Mo or MoW, Cr, Al or Al alloy and Ta is formed on the ohmic contactlayer pattern 55 and 56. The data wire has a data-line 62 including asource electrode 65 and extending in the vertical direction, a data pad64 connected to an end of data line 62 and transmitting image signalfrom an external circuit to the data line 62. The data wire also has adrain electrode 66 located at the opposite side of the source electrode65 with respect to the gate electrode 26, a pixel electrode line 69extended from the drain electrode 66 and parallel with the common line27, and pixel electrodes 68 which are branches of the pixel electrodeline 69 and parallel with the common electrode 28. The pixel electrode68 and the common electrode 28 are located by turns and generateelectric fields therebetween when voltages applied. The pixel electrode68 may be overlapped with the common electrode line 27 to form a storagecapacitor.

The ohmic contact layer pattern 55 and 56 plays a role to reduce thecontact resistance between the semiconductor pattern 42 and the datawire 62, 64, 65, 66, 68 and 69, and has the same layout as the data wire62, 64, 65, 66, 68 and 69. The semiconductor pattern 42 has the samelayout as the data wire 62, 64, 65, 66, 68 and 69 and the ohmic contactlayer pattern 55 and 56 except for the channel part between the sourceelectrode 65 and the drain electrode and 66.

A passivation layer 80 is formed on the data wire 62, 64, 65, 66, 68 and69. The passivation layer 80 has contact holes 82, 83 and 84respectively exposing the data line 62, gate pad 24 and the data pad 64.The passivation layer 80 may be made of SiNx or an organic insulatorsuch as an acrylic resin.

A conductive pattern 72, 73, 74, 75 and 76 is formed on the passivationlayer 80. The conductive pattern includes a redundant data line 72covering the data line 62, a redundant data pad 74 covering the data pad64 and a redundant gate pad 73 covering the gate pad 24.

Now, a manufacturing method of a thin film transistor array panelaccording to the eighth embodiment of the present invention will bedescribed with reference to the FIGS. 39A to 41C and FIGS. 36 to 38mentioned above.

At first, as shown in FIGS. 39A to 39C, a layer of conductor such as ametal is deposited on a substrate 10 by such a method as sputtering to athickness of 1,000 Å to 3,000 Å. A gate wire including a gate line 22, agate pad 24 and a gate electrode 26 and a common electrode wireincluding a common line 27, common electrodes 28 and a common pad (notshown) are formed by dry etch or wet etch using the first mask.

Next, as shown in FIGS. 40A to 40C, a gate insulating layer, asemiconductor layer and an ohmic contact layer are sequentiallydeposited to have the thickness of 1,500 Å to 5,000 Å, 500 Å to 2,000 Åand 300 Å to 600 Å respectively by such a method as chemical vapordeposition (CVD). Then, a metal layer is deposited to have a thicknessof 1,500 Å to 3,000 Å by such a method as sputtering. The metal layer,the ohmic contact layer, the semiconductor layer are patterned to form adata wire 62, 64, 65, 66, 68 and 69, and the ohmic contact pattern 55and 56 and the semiconductor layer pattern 42 thereunder in the secondphotolithography step. At this time, the semiconductor layer pattern 42remains under the data wire 62, 64, 65, 66, 68 and 69 and between thesource electrode 65 and the drain electrode 66. In the other area, thesemiconductor layer is totally removed. The portion of semiconductorlayer pattern 42 between the source electrode 65 and the drain electrode66 is exposed and forms a channel of the TFT. To obtain this, it isnecessary to fabricate a PR pattern of which portion corresponding tothe channel has a thickness thinner than that of the portioncorresponding to the data line. Such a PR pattern may be obtained byusing a photomask of which portion corresponding to the channel has alower transmittance than elsewhere.

After forming the PR layer pattern that has a variant thickness, thelayers are etched using the PR layer pattern as etch mask. First, theexposed portion of the metal layer is etched by such a method as wetetch. Then, the thin PR layer on the channel, the exposed ohmic contactlayer and the semiconductor layer thereunder except for the portionunder the data wire are etched at the same time. Therefore, the metallayer of the channel part is exposed, the thick PR layer on the datawire is stripped to a certain thickness and the gate insulating layer 30of elsewhere is exposed. Next, the metal layer of the channel part iswet etched exposing the ohmic contact layer thereunder. The exposedohmic contact layer is dry etched out to complete a pattern.

Next, as shown in FIGS. 41A to 41C, a passivation layer 80 of over 3,000Å is formed by CVD (chemical vapor deposition) of SiNx or by spincoating an organic insulating layer and patterned along with the gateinsulating layer 30 using the third mask. By this patterning, the gatepad 73, the data pad 74 and the data line 62 are exposed.

As the last step, a conductor layer is deposited to a thickness of 400 Åto 500 Å and patterned to form a conductive pattern 72, 73 and 74 asshown in FIGS. 41A to 41C using the fourth mask.

As described above, in the eighth embodiment, the number ofphotolithography step is reduced by patterning the semiconductor layeralong with the data wire 62, 64, 65, 66, 68 and 69 at the same time.

By the present invention, the manufacturing process of a thin filmtransistor panel for a liquid crystal display is efficiently simplified.At the same time, the gate pads and the data pads are protected. Inaddition, the leakage current of an LCD is efficiently reduced.

In the drawings and specification, there have been disclosed typicalpreferred embodiments of the present invention and, although specificterms are employed, they are used in a generic and descriptive senseonly and not for purposes of limitation, the scope of the inventionbeing set forth in the following claims.

1.-53. (canceled)
 54. A thin film transistor array panel comprising: aninsulating substrate; a plurality of gate lines; a gate insulating layercovering the gate lines; a plurality of semiconductors on the gateinsulating layer; a plurality of ohmic contacts on the semiconductors; aplurality of data lines and source electrodes connected to the datalines, and a plurality of drain electrodes separate from the sourceelectrodes on the ohmic contacts; and a plurality of conductiveelectrodes electrically connected to the drain electrodes, wherein thesemiconductors except for the portions between the source electrodes andthe drain electrodes substantially have the same plane shapes as thedata lines, the source electrodes and the drain electrodes.
 55. The thinfilm transistor array panel of claim 54, further comprising a pluralityof common electrodes formed on the insulating substrate.
 56. The thinfilm transistor array panel of claim 55, wherein the common electrodesare formed with the same layer as the gate lines.
 57. The thin filmtransistor array panel of claim 54, further comprising a passivationlayer covering the data lines and the drain electrodes.
 58. The thinfilm transistor array panel of claim 57, wherein a passivation layer isformed under the conductive electrodes.
 59. The thin film transistorarray panel of claim 54, the conductive electrodes are pixel electrodes.